1. Technical Field
The present invention relates to an efficient multi-chip data detection technique for decoding any symmetric differential phase shift keying (SDPSK) or symmetric differential quadriphase shift keying (SDQPSK) data, and more particularly, relates to a multi-chip data detector design for symmetric differential phase shift keying (SDPSK) or symmetric different quadriphase shift keying (SDQPSK) modulation format using multiple-chip observation intervals to improve performance.
2. Related Art
Generally, there are several data detection techniques known for detecting data over a mobile channel. A common technique is known as coherent detection for best system performance. An attractive alternative to coherent detection for applications where system simplicity and robustness of implementation take precedence over achieving the best system performance may be differential data detection technique. Differential data detection technique may reduce significant performance losses over a multipath fading channel.
In the past, conventional differential detection of data of different phase shift keying modulation formats has been accomplished by comparing the received phases of two successive symbol intervals and making a multilevel decision based on the difference between the two phases. However, the conventional symbol-to-symbol differential detection commonly suffers from a performance penalty (additional required signal-to-noise ratio SNR at a given bit error rate) when compared to ideal coherent detection. The amount of the performance penalty may be proportional to the number of phases and may be significant when the number of phases is substantially high.
One way of enhancing the performance of the conventional symbol-to-symbol differential detection technique while maintaining a simple and robust differential detection implementation is to use a multiple symbol observation interval longer than two symbol intervals while at the same time making a joint decision on several symbols simultaneously as opposed to symbol-to-symbol detection. General concepts and performance of multiple symbol (multi-chip) differential detection are disclosed in xe2x80x9cMultiple-Symbol Differential Detection Of MPSK,xe2x80x9d by D. Divsalar and M. K. Simon, IEEE Transactions on Communications, March 1990, which is incorporated by reference herein. Basically, multi-chip differential detection technique observes the symbols over a longer interval and yields a significant performance gain with lower error rate. Various multi-chip differential detection schemes for symmetric differential phase shift keying (SDPSK) modulation formats such as a 2-chip differential detection, a 3-chip differential detection, and a 4-chip differential detection with xe2x80x9cmajority rulexe2x80x9d processing are described in xe2x80x9cMulti-Symbol Detection Schemes for SDPSK Demodulation,xe2x80x9d by D. Sammons, IOC, MDR-02-M1001-118, November 1992, which is incorporated by reference herein. The 4-chip differential detection may offer the most significant performance gain with little impact on hardware complexity. However, if the observation interval is further increased, the performance of the differential detection may improve but the hardware complexity may grow dramatically.
In order to perform multi-chip detection, the received phase string is compared with a set of stored ideal patterns, and a decision is made as to which symbol set was received. There are two methods currently available for multi-chip differential detection. A first method relates to a table lookup technique to index into a stored set of symbol sets. A read-only-memory (ROM) may be used for mapping data bits and parity bits of the received vector relative to ideal vectors for data detection. A second method relates to a one-by-one comparison technique to compare the received phases with ideal pattern and to detect based on maximum likelihood. However, each of these techniques is both hardware and power intensive.
Accordingly, various embodiments of the present invention are directed to an improved, more efficient multi-chip differential detection technique and a multi-chip data detector hardware for decoding data of a symmetric differential phase shift keying (SDPSK) modulation format with significant performance gain and efficient hardware implementation in terms of gate count, power consumption and processing speed.
In accordance with various embodiments of the present invention, an improved data detector for decoding an incoming data modulated in either a symmetric differential phase shift keying (SDPSK) format or a symmetric differential quadriphase shift keying (SDQPSK) format is provided. The data detector comprises a phase-difference encoder arranged to encode phase-differences of at least four consecutive input phases of incoming modulated data during a multi-chip observation interval to produce a received vector of a predetermined number of data bits and parity bits; a decoder arranged to decode the received vector to produce multiple bit decisions by mapping the received vector with a set of ideal vectors; and a majority voter arranged to choose a bit estimate from the multiple bit decisions by way of a majority rule to produce a final detected symbol from the incoming modulated data during the multi-chip observation interval.
If the incoming data is modulated in a symmetric differential phase shift keying (SDPSK) format from a transmitter, the predetermined number of the received vector corresponds to 3 data bits and 3 parity bits. The multi-chip observation interval corresponds to a 4-chip observation interval with each symbol containing 1 bit, and the set of ideal vectors corresponds to eight (8) phase transition possibilities over the 4-chip observation interval.
The phase-difference encoder block of the SDPSK data detector comprises a plurality of subtractors and XOR gates arranged to determine the phase differences of an input phase of incoming modulated data delayed by one-chip, two-chips and three-chips during the 4-chip observation interval, and to encode the phase differences to produce the received vector of 6-bits.
The decoder block of the SDPSK data detector comprises a vector unit arranged to provide the received vector from the phase-difference encoder block for decoding operations; a first selection unit arranged to receive the data bits of the received vector; a first ROM look-up table arranged to provide the parity bits of the ideal vector having the same data bits; a first mismatch counter arranged to count the number of mismatches between the lookup output with the parity bits of the received vector; a second selection unit arranged to receive the parity bits of the received vector; a second ROM arranged to provide the data bits of the ideal vector having the same parity bits; a second mismatch counter arranged to count the number of mismatches between the lookup output with the data bits of the received vector; and a comparator arranged to pick the ideal vector that is closest to the received vector so as to produce the parallel multiple bit decisions.
The majority voter block of the SDPSK data detector is used to vote on the three decisions of the same symbol. The majority voter block requires three AND gates and one OR gate.
If the incoming data is modulated in a symmetric differential quadri-phase shift keying (SDQPSK) format, the predetermined number of the received vector corresponds to 12-bits of 6 data bits and 6 parity bits. The multi-chip observation interval corresponds to a 4-chip observation interval with each symbol containing 2-bits, and the set of ideal vectors corresponds to sixty-four (64) phase transition possibilities over the 4-chip observation interval.
The phase-difference encoder block of the SDQPSK data detector comprises a plurality of subtractors and XOR gates arranged to determine the phase differences of an input phase of incoming modulated data delayed by one-chip, two-chips and three-chips during the 4-chip observation interval, and to encode the phase differences to produce the received vector.
The decoder block of the SDQPSK data detector comprises a vector unit arranged to provide the received vector of 12-bits from the phase-difference encoder block for decoding operations; a first plurality of selection unit arranged to receive the top 6-bits (data bits) of the received vector and the successive complements of the top 6-bits of the received vector; a first plurality of ROM look-up tables arranged to provide the parity bits of the ideal vector *having the same data bits; a first plurality of mismatch counters arranged to count the number of mismatches between the lookup outputs with the parity bits of the received vector; a second plurality of selection units arranged to receive the bottom 6-bits (parity bits) of the received vector and successive complements of the bottom 6-bits of the received vector; a second plurality of ROM look-up tables arranged to provide the data bits of the ideal vector having the same parity bits; a second plurality of mismatch counters arranged to count the number of mismatches between the lookup outputs with the data bits of the received vector; and a comparator arranged to pick the ideal vector that is closest to the received vector of 12-bits so as to produce parallel detected symbols from the incoming modulated data.
The present invention is more specifically described in the following paragraphs by reference to the drawings attached only by way of example.